Edaptive Training Solutions
Creating the Next Generation Microelectronics Verification Workforce
The Edaptive Computing Training Program comprises a suite of training courses covering the theory of different verification methodologies and their application to relevant design use cases. Each course provides interactive sessions with instructors and students (on-site or online), an online platform to access the pertinent tools, and hands-on lab exercises to provide experience in applying verification methodologies to the student’s own designs.
ECI Formal Verification Training
This 3-day introduction to formal verification covers the theory of formal methods and their application to hardware verification methodologies. It addresses inherent differences between formal verification and simulation-based approaches, requirements versus specifications, propositions, temporal assertions, sequential extended regular expressions, and finite state machines. It applies different formal languages to develop specifications for a wide variety of designs and use cases.
For more details, visit our Formal Training page.
Introductory OneSpin Training: This 4-day training addresses the setup, methodology, and deployment of applications (Apps) in the OneSpin tool suite to address a wide variety of verification tasks with formal methods and hardware model checking. The training is offered three times per year, online and on-site (conditions permitting).
- Day 1 introduces the OneSpin tool and environment, setup, and steps for design verification. Lessons cover autochecks and the Apps available in the OneSpin tool, including protocol checking, register mapping, and SoC connectivity.
- Day 2 delves into SystemVerilog Assertions (SVAs) and the methodology for effective assertion-based formal verification.
- Day 3 focuses on formal sequential equivalence checking (SEC) between RTL and netlist designs. It covers setting up designs with the OneSpin’s EC-FPGA and EC-ASIC tools and executing the EC workflow, highlighting mapping, comparing, and debugging steps.
- Day 4 addresses fault injection, propagation, and analysis in RTL and netlist designs using OneSpin’s suite of safety Apps.
For more details, visit our OneSpin Tools Training page.
Radix-S Training: This one-day introductory Tortuga Logic Radix-S class walks students through the use of the tool, debug methodologies, and ways to write effective Sentinel Security Rules to trace information flow through a design. Students will then be challenged to explore these foundational concepts in more detail through lectures and hands-on labs examining concepts such as Advanced Encryption Standard (AES) subsystem key leakage, protected memory access violations, firmware misconfiguration errors, and RISC-V system-level verification.
For more details, visit our Radix-S Training page.
Synopsys Tools Training
Synopsys VCS/Verdi Training: This training series addresses the setup, tool flow/methodology, and the application of the Synopsys Tools Suite to address a wide variety of tasks with directed testing and emulation verification methodologies. The training will be offered three times per year, online and on-site (conditions permitting).
- Day 1 - VCS Training: This training will cover the usage of Synopsys VCS simulator. We will cover the compilation process, libraries, simulation and other capabilities of using the tool. This training will be 4 hours long. Attendees can interface directly with the software through TSS. After this training, you will be able to compile VHDL and Verilog designs and simulate those designs with Synopsys VCS.
- Day 2 - Verdi Training: This training will cover the usage of Synopsys Verdi, an advanced interactive and post-process simulation debug tool. Synopsys Verdi is a common GUI unifying many Synopsys products including Simulation, Formal, Emulation and Static Analysis. This training will be 4 hours long. Attendees can interface directly with the software through TSS. The first half of the training will be applicable to all users while the second half of the training will focus on usage for verification engineers. After this training you will have a background to view of RTL designs through waveforms, schematics and annotated source code. You will also be exposed to many of the modern verification features that Verdi exposes to interact with UVM testbenches.
For more details, visit our Synopsys Tools Training page.
ECI Security Verification TrainingThis 3-day introductory training addresses the use of different verification methodologies to address security-based problems. The course highlights the security vulnerability landscape and discusses the different classes of security vulnerabilities. It covers the specification and verification of security properties using assertion-based and information-flow-based verification methods. Its interactive lab exercises highlight these security verification methodologies on a broad variety of design examples covering a wide range of security contexts.
As a RISC-V International training partner, ECI provides a 1-day training covering (a) formal verification of RISC-V cores (pipeline, correct execution of standard and custom instructions, interrupts, exceptions, and flushes) using OneSpin’s Processor Integrity Solution; and (b) verification of security properties (maintaining security in a design’s control and status registers, validating the functionality of physical memory protections, and identifying side-channel vulnerabilities) using Tortuga Logic tools, combined with emulation and simulation.
Edaptive Computing, Inc (ECI) is a RISC-V International training partner.